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1 power mosfet features ? halogen-free according to iec 61 249-2-21 definition ? dynamic dv/dt rating ? repetitive avalanche rated ? surface mount (irfrc20, sihfrc20) ? straight lead (irfuc20, sihfuc20) ? available in tape and reel ?fast switching ? ease of paralleling ? compliant to rohs directive 2002/95/ec no tes a. repetitive rating; pulse widt h limited by maximum junction temperature (see fig. 11). b. v dd = 50 v, starting t j = 25 c , l = 37 mh, r g = 25 , i as = 2.0 a (see fig. 12). c. i sd 2.0 a, di/dt 40 a/s, v dd v ds , t j 150 c. d. 1.6 mm from case. e. when mounted on 1" square pcb (fr-4 or g-10 material). pr od uct summary v ds (v ) 6 00 r ds(on ) ( )v gs = 10 v 4.4 q g (max.) (nc) 18 q gs (nc) 3.0 q gd (nc ) 8.9 conf iguration single n-channel mosfet g d s dp ak (t o-252) ipak (to-251) g d s s d g d absolute maximu m ratings t c = 25 c, unless otherwise noted para me ter symbol limit unit drain-source voltage v ds 600 v gate-source vo ltage v gs 20 continuous drain cu rrent v gs at 10 v t c = 25 c i d 2.0 a t c = 100 c 1.3 pul sed drain current a i dm 8.0 linear derating factor 0.33 w/ c linear derating factor (pcb mount) e 0.020 s ing le pulse avalanche energy b e as 74 mj re petitive avalanche current a i ar 2.0 a repetitive avalanche energy a e ar 4.2 m j maximum power dissipation t c = 25 c p d 42 w maximum power dissipation (pc b mount) e t a = 25 c 2.5 p eak diode recovery dv/dt c dv/dt 3.0 v /ns operating junction and storage temperature range t j , t stg - 55 to + 150 c soldering recommendations (p eak temperature) for 10 s 260 d * p b containing terminations are not rohs compliant, exemptions may apply dt81 www.din-tek.jp
2 not e a. when mounted on 1" square pcb (fr-4 or g-10 material). notes a. repetitive rating; pulse widt h limited by maximum junction temperature (see fig. 11). b. pulse width 300 s; duty cycle 2 %. t h ermal resistance ratings parameter symb ol mi n. typ. max. unit maximum junction-to-ambient r thja - - 110 c/ w maximum junction-to-ambient (pcb mount) a r thja -- 5 0 maxi mum junction-to-case (drain) r thj c -- 3 . 0 specific ations t j = 25 c, unless otherwise noted parameter s y mbol test condi tions min. typ. max. unit sta t ic drain-source brea kdown voltage v ds v gs = 0 v, i d = 250 a 600 - - v v ds tem perature coefficient v ds /t j r eference to 25 c, i d = 1 ma - 0.88 - v/c gate-source threshold voltage v gs(t h) v ds = v gs , i d = 250 a 2 .0 - 4.0 v gate-source leakage i gss v gs = 20 v - - 100 na zero gate voltage drain current i dss v ds = 600 v, v gs = 0 v - - 100 a v ds = 480 v, v gs = 0 v, t j = 125 c - - 500 drain-source on-state resistance r ds(on ) v gs = 10 v i d = 1 . 2 a b -- 4 .4 forward transconductance g fs v ds = 50 v, i d = 1 .2 a 1 .4 - - s dynam i c input capacitance c iss v gs = 0 v, v ds = - 25 v, f = 1.0 mhz, see fig. 5 - 350 - pf output capacitance c oss -48 - reverse transfer capacitance c rss -8 . 6- total gate charge q g v gs = 10 v i d = 2.0 a , v ds = 360 v, see fig. 6 and 13 b -- 1 8 nc gate-source charge q gs -- 3 .0 gate-drain charge q gd -- 8 .9 turn-on delay time t d(on ) v dd = 300 v , i d = 2.0 a, r g = 1 8 , r d = 135 , see fig. 10 b -1 0 - ns rise time t r -2 3 - turn-off delay time t d(of f) -3 0 - fall time t f -2 5 - internal drain inductance l d b e tween lead, 6 mm (0.25") from package and center of die contact -4.5- nh internal source inductance l s -7 . 5- d r ain-source body diode characteristics continuous source-dr ain diode current i s mosfet symbol sho w ing the integral reverse p - n junction diode --2.0 a pulsed diode forward current a i sm -- 8 .0 body diode voltage v sd t j = 2 5 c, i s = 2.0 a, v gs = 0 v b -- 1 .6v body diode reverse recovery time t rr t j = 25 c, i f = 2.0 a, di/dt = 100 a /s b - 290 580 ns body diode reverse recovery charge q rr - 0.67 1.3 c forward turn-on time t on intrinsic turn-on time is negl igible (turn-on is dominated by l s and l d ) d s g s d g dt81 www.din-tek.jp
3 t y pical characteristics 25 c, unless otherwise noted fi g. 1 - typical output characteristics, t c = 2 5 c fig. 2 - typical output characteristics, t c = 150 c fig . 3 - typical transfer characteristics fig. 4 - normalized on-r esistance vs. temperature dt81 www.din-tek.jp
4 fi g. 5 - typical capacitance vs. drain-to-source voltage fig. 6 - typical gate charge vs. gate-to-source voltage fig. 7 - typical source-drain diode forward voltage fig. 8 - maximum safe operating area dt81 www.din-tek.jp
5 fi g . 9 - maximum drain current vs. case temperature fig. 10a - switching time test circuit fig. 10b - switching time waveforms fig. 11 - maximum effective transient thermal impedance, junction-to-case pulse width 1 s duty factor 0.1 % r d v gs r g d.u.t. 10 v + - v ds v dd v ds 90 % 10 % v gs t d(on) t r t d(off) t f dt81 www.din-tek.jp
6 fi g. 12a - unclamped inductive test circuit fig. 12b - unclamped inductive waveforms fig. 12c - maximum avalanche energy vs. drain current fig. 13a - basic gate charge waveform fig. 13b - gate charge test circuit r g i as 0.01 t p d.u.t l v ds + - v dd 10 v va r y t p to obtain required i as i as v ds v dd v ds t p q gs q gd q g v g charge v gs d.u.t. 3 ma v gs v ds i g i d 0.3 f 0.2 f 50 k 12 v current regulator current sampling resistors same type as d.u.t. + - dt81 www.din-tek.jp
7 fig. 14 - for n-chann el p.w. period di/dt diode recovery dv/dt ripple 5 % body diode forward drop re-applied voltage reverse recovery current body diode forward current v gs = 10 v a i sd driver gate drive d.u.t. l sd waveform d.u.t. v ds waveform inductor current d = p.w. period + - + + + - - - peak diode recovery dv/dt test circuit v dd ? dv/dt controlled by r g ? driver same type as d.u.t. ? i sd controlled by duty factor d ? d.u.t. - device under test d.u.t. circuit layout considerations low stray inductance ? ground plane ? low leakage inductance current transformer r g note a. v gs = 5 v for logic level device s v dd dt81 www.din-tek.jp
1 to-252aa (h igh volt age) notes 1. packa ge body sizes exclude mold flash, protrusion or gate bu rrs. mold flash, protrusion or gate burrs shall not exceed 0.10 mm per side. 2. package body sizes determined at the outermo st extremes of the plastic body exclusive of mold flas h, gate burrs and interlea d flash, but including any mismatch between the top and bottom of the plastic body. 3. the package top may be smaller than the package bottom. 4. dimension "b" does not include dambar prot rusion. allowable dambar protrusion shall be 0.10 mm total in excess of "b" dimens ion at maximum material condition. the dambar cannot be located on the lower radius of the foot. e b3 l3 l4 b2 e b d h e1 d1 a c2 l1 l2 c a1 l millimeters inches d i m. min. max. min. max. e 6.40 6.73 0.252 0.265 l 1.40 1.77 0.055 0.070 l1 2.743 ref 0.108 ref l2 0.508 bsc 0.020 bsc l3 0.89 1.27 0.035 0.050 l4 0.64 1.01 0.025 0.040 d 6.00 6.22 0.236 0.245 h 9.40 10.40 0.370 0.409 b 0.64 0.88 0.025 0.035 b2 0.77 1.14 0.030 0.045 b3 5.21 5.46 0.205 0.215 e 2.286 bsc 0.090 bsc a 2.20 2.38 0.087 0.094 a1 0.00 0.13 0.000 0.005 c 0.45 0.60 0.018 0.024 c2 0.45 0.58 0.018 0.023 d1 5.30 - 0.209 - e1 4.40 - 0.173 - 0' 10' 0' 10' ecn: s-81965-rev. a, 15-sep-08 dwg: 5973 package information www.din-tek.jp
1 to-251aa ( h igh voltage) no tes 1. dimensioning and toler ancing per asme y14.5m-1994. 2. dimension are shown in inches and millimeters. 3. dimension d and e do not include mold flash. mold flash s hall not exceed 0.13 mm (0.005") per side. these dimensions are mea sured at the outermost extremes of the plastic body. 4. thermal pad contour optional with dimensions b4, l2, e1 and d1. 5. lead dimension uncontrolled in l3. 6. dimension b1, b3 and c1 apply to base metal only. 7. outline conforms to jedec outline to-251aa. base metal plating b1, b3 (b , b2) c1 (c) section b - b and c - c d a c2 c lead tip 5 5 (datum a) ther mal p ad e1 4 d1 vie w a - a a1 a a c seating plane c c b b 1 2 b 4 4 4 3 5 l1 l l3 3 x b2 3 x b 3 b4 e 2 x e 0.010 c b m a 0.25 0.010 b a 0.25 l2 a c m mill imeters inc hes millimeters inches dim. min. max. min. max. dim. min. max. min. max. a 2.18 2.39 0.086 0.094 d1 5.21 - 0.205 - a1 0.89 1.14 0.035 0.045 e 6.35 6.73 0.250 0.265 b 0.64 0.89 0.025 0.035 e1 4.32 - 0.170 - b1 0.65 0.79 0.026 0.031 e 2.29 bsc 2.29 bsc b2 0.76 1.14 0.030 0.045 l 8.89 9.65 0.350 0.380 b3 0.76 1.04 0.030 0.041 l1 1.91 2.29 0.075 0.090 b4 4.95 5.46 0.195 0.215 l2 0.89 1.27 0.035 0.050 c 0.46 0.61 0.018 0.024 l3 1.14 1.52 0.045 0.060 c1 0.41 0.56 0.016 0.022 1 0' 15' 0' 15' c2 0.46 0.86 0.018 0.034 2 25' 35' 25' 35' d 5.97 6.22 0.235 0.245 ecn: s-82111-rev. a, 15-sep-08 dwg: 5968 package information www.din-tek.jp
3 application note recommende d minimum pads for dpak (to-252) 0.420 (10.668) recommended mi nimum pads dimensions in inches/(mm) 0.224 (5.690) 0.180 (4.572) 0.055 (1.397) 0.243 (6.180) 0.087 (2.202) 0.090 (2.286) return to index application note www.din-tek.jp
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